Course description
VERSEC is an intensive, three-day, hands-on short course designed to equip participants with the knowledge and practical skills needed to apply Machine Learning (ML) and Large Language Models (LLMs) to the domains of chip design, functional verification, and hardware security.
The course is tailored primarily for industry professionals but is also open to academic participants, including faculty, researchers, and students. Through a combination of lectures, live demos, and exercise-driven labs, participants will learn how ML and LLMs can accelerate and enhance various aspects of the hardware design and validation pipeline—from Verilog generation and verification automation to vulnerability detection and secure design repair.
Registration Overview
- This course is delivered face-to-face with a total of 21 hours (CEU 2.1, PDH 21)
- Chip designers, verification engineers, hardware security professionals, and researchers interested in the application of ML and LLMs to semiconductor design and validation workflows.
- The course fee is $1,500 per person.
- Please direct questions about the offering to Dr. Jeyavijayan Rajendran. For questions related to the registration process, please contact TEES EDGE.
Learning Objectives
How Machine Learning (ML) and Large Language Models (LLMs) can be applied to:
- Chip design
- Functional verification
- Hardware Security Techniques
- Generate Assertions
- Creating Testbenches
- Coverage improvement
- Debug
Who Should Attend
This course is designed for professionals and researchers in chip design, verification, and hardware security who aim to apply large language models to real-world verification and security workflows. It is ideal for RTL designers, verification engineers (UVM/testbench, coverage, formal), and hardware security practitioners focused on RTL vulnerability discovery and secure design repair. EDA tool developers and applied AI teams building LLM-assisted flows, as well as technical managers/architects evaluating roadmap impact, will benefit. Graduate students and faculty in computer engineering, EDA, or hardware security are welcome; familiarity with Verilog/SystemVerilog and basic simulation/verification concepts is recommended.
Target Audience
- Chip Design and Verification Engineers Professionals working on RTL development, simulation, testbench creation, and functional or formal verification who are interested in accelerating workflows using ML and LLMs.
- Hardware Security Engineers focused on RTL security analysis, vulnerability detection, and secure design, looking to explore AI-assisted techniques.
- EDA Tool Developers and Researchers: Those building or integrating new capabilities into verification and security tools, especially with AI/ML components.
- Managers and Architects in the semiconductor industry.
- Individuals responsible for innovation, tool evaluation, or roadmap planning within chip design teams.
- Graduate Students and Academic Researchers, especially those in computer engineering, EDA, AI for hardware, or hardware security, are looking to upskill and explore industry-relevant ML and LLM applications.